Unity Chip Planner
Made for Custom Digital
Custom designers face unique challenges such as large hard-IP blocks, analog content, few metal layers available for routing. At leading-edge nodes (28 nm and below), process rules constrain designs in new ways, and the extreme aspect ratios of the routed wires and highly resistive metals make understanding parasitics critical. Pulsic has applied insights gained in over 10 years of work with leading-edge custom designers to develop Unity Chip Planner to address the unique needs of custom design.
A new approach
Automated, hierarchical floorplanners are a standard part of the digital design flow. However, they don’t address the unique needs of custom design. So, until now, many custom design teams have struggled with bottom-up, manual assembly methodologies that lack a global understanding of a chip’s routing congestion and top-level parasitic data for simulation until the chip is almost complete. With these manual approaches, lack of automation and hierarchy management waste design effort and silicon resource. The frequent netlist changes that are a natural part of a leading-edge design process are difficult to manage manually and can cause major delays.
Faster Design Closure
By providing a high level of automation, Unity Chip Planner gives accurate results quickly and enables custom design teams to respond to netlist changes quickly and easily. Unity Chip Planner provides all the necessary tools and technologies within a fully integrated floorplanning environment. The guided flow offered in Unity Chip Planner helps ensure faster design closure with successful results, every time.
Rapid Floorplan Prototyping
Efficient, effective custom design floorplanning requires a series of top-down optimizations, followed by a bottom-up optimization, that determine pin placement in consideration of the block placement at lower levels of hierarchy, then use those pin placements as the backbone of communication between levels of hierarchy.
Tight design cycles rarely afford custom designers the time to explore different floorplans to find the best fit for the die area. The Unity Chip Planner has a flexible and easy-to-configure interface that enables designers to explore different packages and to prototype multiple floorplan topologies quickly to find the optimal use of the die area allocated for the design.
Achieve design closure faster with the first and only top down hierarchical floorplanner for custom design
Explore options and implement floorplans rapidly with accurate area and parasitic data
Obtain accurate parasitics for early simulation and static timing analysis
Execute ECOs quickly and precisely.
Hierarchical and pseudo-hierarchical floorplanning for custom design
Hierarchical area estimation, including custom digital and analog estimation
Automatic block placement and softblock shaping
Hierarchical automatic pin placement and sorting optimization
Intelligent, router-aware pin placement for efficient top-level routing